Method of making a three dimensional circuit with an imprint tool

ABSTRACT

Imprinting tools that include a female master tool and a male working tool are used to create three-dimensional circuits. The female tool is used to create multiple male tools that are metallized and pressed into a substrate transferring the metallization to the substrate. Metallization on prominences of the male tool can be selectively removed to create vias, blind vias, vertical traces and other selectively non-metallized regions for interconnect circuitry. The process is used to create circuitry that includes narrow, high aspect ratio traces having reduced parasitic capacitance to adjacent circuit features.

CROSS-REFERENCE TO RELATED APPLICATIONS

Not Applicable.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to a method to manufacture high aspectratio traces, tools used in the method and electronic circuit structurescreated with such traces.

2. Related Background Art

Manufacturers of popular portable electronic equipment such as cellphones and personal computers have placed enormous stresses on theinterconnect industry. Hybrid circuit and printed circuit board (PCB)customers continue to demand smaller form factors, higher performanceand more features. The two primary forces driving these requirements arethe continued increase of semiconductor density and cost. Consequently,there is pressure on the interconnect industry to provide: 1) finergeometries (10 μm and below), 2) better line width control, 3) thinnerdielectrics, and 4) better electrical performance. Process costs need tobe lower than current high-density solutions. Additionally, entrybarriers for the production processes necessary to achieve theserequirements should be low and allow smaller manufacturers to producehigh-quality and high-density substrates, preferably using existingequipment and manufacturing processes.

Imprint patterning presents an elegant solution to the contradictoryrequirements of high performance and low entry barriers. Imprintpatterning replaces alternative and more expensive photolithography andlaser drilling processes with a simple and cost-effectivemicroreplication step. It produces features for all circuit traces andinterconnect vias for a particular layer simultaneously. It avoids themasking and registration steps in conventional PCB manufacturingprocesses that contribute to density constraints and scrap. Importantly,it can be implemented in virtually any printed circuit shop with minimaladditional equipment and process development expense. The basic toolsand methods for imprint patterning of PCBs are described in U.S. Pat.Nos. 5,334,279; 5,390,412; 5,451,722; 6,005,198; 6,460,247 and RE38,579;all by the inventor and all hereby incorporated by reference.

Although imprint patterning produces interconnect circuits at lower costand with higher circuit density, it has heretofore resulted in a typicalmultilayer structure having low aspect ratio traces (wider than they aretall) that produce large parasitic capacitances between traces ondifferent layers or between traces and ground or power planes. Theseparasitic capacitances limit electronic performance of the assembledcircuitry in that they provide unintended spurious signal coupling pathsbetween isolated traces that can cause excessive system noise or causeexcessive capacitive loading of sensitive circuits that can slow downoperating waveforms.

Prior attempts to reduce these performance limiting parasiticcapacitances have involved reducing trace dimensions while increasinginterlevel dielectric thicknesses. Unfortunately, as experiencedsimilarly in the semiconductor industry, these measures result in addingexpensive, special purpose processes that add significantly to the costof the product, while simultaneously erecting significant entry barriersin the form of new equipment capitalization costs.

Therefore, it is desirable to provide a new and improved imprintpatterning process for PCBs and other interconnect circuits thatincludes the ability to fabricate high aspect ratio traces (taller thanthey are wide) having particularly narrow widths compared to and inaddition to conventional imprinted traces.

DISCLOSURE OF THE INVENTION

Embodiments are described for imprinting tools, processes for makingsuch tools, circuitry and processes for making such circuitry using theimprinting tools. The tools and circuitry are described as beingincorporated into exemplary circuit manufacturing processes and theresultant circuitry. Those skilled in the art will recognize that thesame techniques are applicable to a wide range of interconnectcircuitry. Examples include printed circuit boards, hybrid microcircuitsfabricated using low temperature co-fired ceramic (LTCC) materials andthin film microcircuits such as those used in the construction of thinfilm display devices, including those having touch-screen sensors.

In its simplest embodiment a two-level imprinting tool coated with alayer of conductive material is formed for each interconnect layer.Conventional CAD systems currently used for designing interconnect suchas printed circuit design data can be used. The conductive material isapplied over a release layer such that the conductive material may betransferred to a circuit device during a lamination process. Theconductive material is applied over selected areas of the imprintingtool using pattern plating techniques. In another embodiment conductivematerial is applied through a process of panel plating and selectivelyremoving conductive material from protruding structures or prominenceson the imprinting tool through a buffing or burnishing process. Inanother embodiment the imprinting tool is made using a process of panelplating, followed by a print and etch process to selectively removeconductive material. Imprinting tools for the outer layers are insertedat the multilayer or build-up layer lamination step adjacent to theseparator sheets. After lamination of the outer layers or build-uplayers, the dielectric has recesses or indentations for traces and viasthat are coated with conductive material. A standard desmear processremoves dielectric material at the bottom of the vias for subsequentmetallization and completes an electrical connection from one layer toanother. In one embodiment the prominences on the imprint tool areridges, which correspond to traces in the circuit design. Ridgesproduces indentations shaped as grooves in the imprinted circuit. Themetalized grooves result in high aspect ratio traces in the finishedcircuit. In another embodiment the prominences on the imprint tool arecylindrical, which correspond to pads or locations for through holes inthe circuit design data. Cylindrical prominences on the imprint toolresult in indentations shaped as holes or pits in the imprinted circuitand result in microvias in the finished circuit. Throughout thisspecification grooves and vias can be taken to also mean more generallyindentations. The word “indentations” refers to an imprinted featurethat may have a variety of geometric shapes.

The conductive material removed from the protruding structures on theimprinting tool corresponds to the conductive material that wouldotherwise be deposited at the bottom of the imprint. Thus, conductivematerial is only transferred to the side walls of the imprint resultingin a nearly vertical microtrace having a width determined by thethickness of the conductive material film and a height determined by thedepth of the imprint. Such high aspect ratio microtraces exhibit muchsmaller parasitic capacitance to other horizontal traces and to groundor power planes.

Embodiments are shown that allow use of the vertical traces both asinterconnect in a single layer and interconnect between layers.Interconnect between layers are also referred to as vias. In oneembodiment an imprinting tool having three or more layers is used toprovide multilevel interconnect design possibilities.

In another embodiment pairs of vertical traces are produced for eachtrace in the conventional design data file. The paired traces provideredundant interconnects for each trace.

In another embodiment vertical traces are layered to produce an XY gridof traces on two levels. Methods are shown to selectively interconnectthe traces on the two levels at their intersection point.

The use of microtraces with conventional traces and vias as well as theusual ground and power planes found in multilevel printed circuit boardsleads to a set of circuit elements having unique electronic properties.Embodiments include transmission lines and shielded interconnections andx-y grids for touch-screen devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view of an initial step of making a circuitimprint tool of FIGS. 3 and 3 a.

FIG. 2 and FIG. 2 a are a schematic views of a second step of making thecircuit imprint tool of FIGS. 3 and 3 a, respectively.

FIG. 3 is a cross-sectional view of a circuit imprint tool master thatis constructed in accordance with the present invention.

FIG. 3 a is a cross-sectional view of an intermediate step in making a3-level circuit imprint tool master.

FIG. 3 b is a cross-sectional view of a second intermediate step inmaking a 3-level circuit imprint tool master.

FIG. 3 c is a cross-sectional view of a 3-level circuit imprint toolmaster that is constructed in accordance with the present invention.

FIG. 4 is a schematic view of a female circuit imprint tool master.

FIG. 4 a is a schematic view of a female 3-level circuit imprint toolmaster.

FIG. 5 is a cross sectional view of a male 3-level circuit imprint toolillustrating the male circuit imprint tool formed against a femalecircuit imprint tool master.

FIG. 5 a is a cross sectional view of a male 3-level circuit imprinttool electroformed against a non-metalized female circuit imprint toolmaster.

FIG. 6 is a cross sectional view of a male circuit imprint tool afterreleasing it from the female circuit imprint tool master.

FIG. 6 a is a cross sectional view of a 3-level male circuit imprinttool after releasing it from the female circuit imprint tool master.

FIG. 7 is a cross sectional view of a male circuit imprint tool beingconstructed in accordance with one embodiment of the present invention.

FIG. 8 is a cross sectional view of a male circuit imprint tool which isconstructed in accordance with the present invention, illustrating themale circuit imprint tool with a conductive material layer and anadhesion layer.

FIG. 9 is a cross sectional view of a male circuit imprint tool in whichthe conductive material and adhesion layers are removed at theprominences of the male circuit imprint tool.

FIG. 9 a is a cross sectional view of a multilevel male circuit imprinttool in which the conductive material and adhesion layers are removed atthe prominences of the male circuit imprint tool.

FIG. 10 is a cross sectional view of making a circuit by imprinting asubstrate with a male circuit imprint tool.

FIG. 10 a is a cross sectional view of making a circuit by imprinting asubstrate with a 3-level male circuit imprint tool.

FIG. 11 is a cross sectional view of an imprinted circuit substrateafter removing the circuit imprint tool.

FIG. 12 is a cross sectional view of circuit embodiments constructed inaccordance with the present invention.

FIG. 12 a is a cross sectional view of additional circuit embodimentsconstructed in accordance with the present invention.

FIG. 13 is a cross sectional view of a two-layer circuit construct inaccordance with the present invention showing microstrip transmissionline embodiments.

FIG. 14 is a cross sectional view of a four-layer circuit construct inaccordance with the present invention showing shielded transmission linestructures.

FIG. 15 is a cross sectional view of a two-layer circuit construct inaccordance with the present invention showing traces in the second layerthat are oriented at right angles with the traces in the first layer.

FIG. 16 is a top view of the two-layer circuit shown in FIG. 15.

FIG. 16 a is a perspective view of an embodiment of the intersection oftwo traces of FIGS. 15 and 16 in which the traces are electricallyinterconnected at the intersection.

FIG. 17 is a flowchart showing the steps in the process of creating acircuit imprint tool.

FIG. 18 is a flowchart showing the steps in the process of creating athree dimensional circuit.

FIG. 19 is a cross sectional view of a circuit constructed in accordancewith an embodiment of the present invention in which the imprintedtraces have been filled with a resist.

FIG. 20 is a cross sectional view of a circuit constructed in accordancewith the present invention wherein the surfaces between traces have beenplated with conductive material.

FIG. 21 is a cross sectional view of a circuit constructed in accordancewith the present invention wherein the plating resist has been removedand showing the gaps that are created between the imprinted traces andthe surface conductive material layer.

FIG. 22 is a top view of the structure of FIG. 21 showing thetwo-dimensional checkerboard pattern useful for touch screenapplications.

FIG. 23 is cross sectional view of a first step in making verticaltraces using an imprint tool.

FIG. 24A is a cross sectional view of a second step from FIG. 23 withthe imprint tool removed.

FIG. 24B is a third step with the process starting with FIG. 23 showingthe imprint grooves filled with dielectric.

FIG. 24C shows a view of finished vertical traces made by the processstarting with FIG. 23.

FIG. 25 shows a view of the traces of FIG. 24C rotated 90 degrees.

FIG. 26A shows an embodiment for selectively making connections betweentraces on different layers.

FIG. 26B shows another embodiment for selectively making connectionsbetween traces on different layers.

FIG. 26C shows a two layer structure embodiment with selectivelyinterconnected traces.

MODES FOR CARRYING OUT THE INVENTION

The process used to fabricate the female imprint tool master and themale imprint tools are illustrated in the flow chart of FIG. 17 andembodiments that include creating circuits are illustrated in FIG. 18.In all following discussions, reference numbers enclosed in parenthesesrefer to the flow charts.

Referring now to the drawings, and more particularly to FIG. 3, there isshown a circuit imprint tool master 308 which is constructed inaccordance with the present invention. The circuit imprint tool master308 generally comprises a plate 309 having a set of valleys or groovessuch as grooves 302, 304, 306 interleaved between a plurality of spacedapart flat portions 301, 303, 305. The tool 308 is configured insubstantially the same shape as the circuit to be imprinted discussedbelow. The circuit imprint tool master 308 is constructed and utilizedas described herein to make a three dimensional circuit having aplurality of sunken conductive pads or traces.

In another embodiment, FIG. 3 c, there is shown a multiple level circuitimprint tool master 321 which is constructed in accordance with thepresent invention. The circuit imprint tool master 321 generallycomprises a plate 318 having a set of valleys or grooves such as grooves322, 313, 315 interleaved between a plurality of spaced apart flatportions. In one embodiment the grooves include single level grooves313, 315 as described above in conjunction with FIG. 3. In anotherembodiment the grooves 322 are comprised of multiple levels. In theexample shown the groove consists of levels 323, 324 each providingadditional interconnect options to those provided by the single level313, 315 grooves. The circuit imprint tool master 321 is configured insubstantially the same shape as the circuit to be manufactured using animprint tool, described below, manufactured from the imprint tool master321. In one embodiment prominences on the circuit imprint toolcorrespond are ridges, which when imprinted produces indentations thatare grooves in the imprinted circuit. Such grooves correspond to tracesin the circuit design. In another embodiment, prominences on the circuitimprint tool are cylindrical shapes, which when imprinted produceindentations that are pits in the imprinted circuits. Such pitscorrespond to through-hole or via locations in the circuit design. Byway of example, FIGS. 11, 12 and 12 a depict circuits, discussed morefully below, that may be created using an imprint tool made from theimprint tool master 321. The circuit imprint tool master 321 isconstructed and utilized to create a circuit imprint tool andsubsequently multi-level interconnect circuits 1203, 1210, 1211 1206,1208, 74, 75,76 as described herein having a plurality of sunkenconductive pads or traces including both horizontally and verticallyoriented interconnect features.

The method of making the circuit imprint tool master is illustrated inFIGS. 1, 2, 3 and the flow charts of FIGS. 17 and 18. The numbers inparenthesis refer to the numbered steps in the flow charts of FIGS. 17and 18.

Considering now the initial step of making the circuit imprint tool 308with reference to FIG. 1. In one embodiment a coating of “photoresist”20 is applied (124) to the top surface of a plate of etchable material22 (120). In the preferred embodiment an etchable copper plate is used,those skilled in the art will understand that other etchable orablatable materials such as other metals, semiconductors, plastics andceramic materials may be utilized. The plate 22 is dimensioned toaccommodate a photo tool 24 (122) of the interconnecting traces requiredfor a given circuit layout. The photoresist 20 is applied to the plateof copper 22 using conventional techniques known in the art, by eithercoating the plate 22 in photoresist or by spraying the photoresistmaterial onto the top surface of the plate 22. Dry-film photoresistapplication techniques are another alternative.

As best seen in FIG. 1, after the photoresist 20 has been applied on thesurface of the plate 22, the photo tool 24 is registered or positionedon the coated top surface of the plate 22. Next, the assembly is exposed(126) to a light, such as a high intensity ultraviolet or laser light 25for a sufficient period of time to expose and solubilize portions of thephotoresist 20. In this regard, a set of emulsion areas 26-28 on thephoto tool 24 protect the select regions photoresist 20 from exposure byblocking the ultraviolet light 25. Those areas of photoresist 20protected from the ultraviolet light 25 are removed or developed outleaving a plurality of windows of photoresist, such as the windows26A-28A, within the photoresist material 20; FIG. 2. In otherembodiments such windows may be formed by a developing solution, lasercut, ablation or other suitable techniques.

The photo tool 24 is then removed from the top surface of the plate 22.The plate 22 is then placed in an etcher (not shown) which dissolves theexposed copper 16, 17, 18 (134). It should be understood that either apositive or negative imaging technique can be used for preparing theplate 22 for etching as will be described hereinafter.

In one embodiment an etching apparatus (not shown) sprays an etchantonto the surface of the plate 22, via the windows 26A-28A, to removeetchable plate material. Nonlimiting exemplary etchant solutions for thepreferred embodiment of a copper plate include ferric chloride, cupricchloride, and peroxide sulfuric. As material is removed from the plate22 a series of grooves or depressions, such as the grooves 302, 304, 306in FIG. 3 are formed in the plate. Residual photoresist material on thesurface of the substrate is then dissolved and removed resulting in thefemale circuit imprint tool master 308 shown in FIG. 3.

In another embodiment a multilevel circuit imprint tool master is madethat provides both traces and interconnect microvias between a pluralityof layers of a multi-level circuit. A first lithography and etch step asdescribed in conjunction with FIGS. 1 and 2 a above produces anintermediate imprint master tool 317 as shown in FIG. 3 a. A secondphotolithography process (124, 126) is accomplished using a separatepattern for the additional level in the master tool. As seen in FIG. 3b, the substrate 318 now with a first set of grooves is further coatedwith photoresist 319 and the photo resist is imaged as described earlierto produce selectively both filled grooves 313, 315 and grooves where aportion of the groove 320 is open to etching or ablation in a subsequentstep. A second etch step (134) then provides the deeper depressions 322.The multilevel imprint tool master 321 seen in FIG. 3 c is seen toconsist of a substrate 318 into which are now etched both single levelgrooves 313, 315 and multi-level grooves 322. In the example shown thegroove has a deeper level 323 and an intermediate level 324 both ofwhich may be used to provide interconnect levels as either microviasconnecting one level to the next or vertical microtraces on a pluralityof levels within the circuit device.

Considering now the female circuit imprint tool masters 308, 321 ingreater detail with reference to FIGS. 3 and 3 c respectively, thefemale circuit imprint tool master 308, 321 (136) is a finished producttool that may be used many times for forming a large number of malecircuit imprint tools, such those shown in FIGS. 6, 6 a and 9, 9 a.Methods of making a male circuit imprint tool from the female circuitimprint tool master are illustrated in FIGS. 4 to 9.

With reference to FIGS. 4 and 4 a, in one embodiment, the process isinitiated by spraying the female master tool 317 with a thin coatingmaterial 402, 42 (138). In the preferred method, the preferred coatingmaterial 402, 42 is an electrically conductive release layer comprisingsilver, a graphite material or a surface passivation. Those skilled inthe art will understand that other coating materials may be utilizedsuch as a low adhesion bathing solution of water and copper sulfate. Inthis regard, a sufficient quantity of coating material 402, 42 isadhered to the surface of the circuit imprint tool 317 to form a coatedtool having a low adhesion bonding surface. In one embodiment, shown inFIG. 4, the imprint tool includes two layers. In another embodiment,shown in FIG. 4 a, the circuit imprint tool comprises more than twolayers.

The coated tool is then subjected to an optional electroless (142)deposition process followed by an electroplating (146) process, such asan electrolytic process. In this regard, the electrolytic process causesa thin layer or coating of conductive material deposited on top of theelectrically conductive release layer 402 to form the conductivematerial transfer layer 40. Those skilled in the art will understandthat platable conductive materials such as copper, nickel, gold andindium tin oxide can be used to form the conductive material layer. Theconductive material transfer layer 40 is then coated with an adhesionpromoting layer (not shown) such as a dendritic oxide.

Next, a combination or assembly 44 as shown in FIG. 5 results fromforming a backing 48, which is molded or laminated (154) to the exposedtop surface of the coated conductive material transfer layer 40. In oneembodiment the backing 48 is a thermoplastic polymeric material moldedto the conductive material transfer layer 40. Nonlimiting examples ofthe thermoplastic include material selected from the group ofpolyethersulphone, polyetherimide, polybutylene terephthalate (PBT), andpolyether ether ketone (PEEK). In another embodiment a thermosetmaterial is used. Nonlimiting examples of thermoset material includeepoxy thermoset polyetherimide, or a polyester based composite of saidthermoset plastic. In another embodiment the backing material may bemetallic. In another embodiment a ceramic backing material is used. Thebacking 48 helps to rigidify the thin conductive material transfer layer40. FIG. 5 shows a multilevel imprint tool master and imprint tool beingformed thereon. Formation of a two level imprint tool from a two levelimprint tool master as pictured in FIG. 4 would be used equivalently fora two level imprint tool but is not shown. Once separated the backedmale circuit imprint tool 50 (FIGS. 6 and 6 a) is formed by removingmechanically and separating it the female tool 22 a from the combination44 (158) (FIG. 5). The electrically conductive release layer 42 has sucha sufficiently low adhesion strength, that the male imprint tool 50 andthe female tool 317, 22 a may be separated mechanically in a relativelyfacile manner.

In another embodiment the male imprint tool 50 is formed of nickel witha conductive material transfer layer by an electroforming process (156).In this regard, the process is as described earlier except a nickelbacking, not shown, replaces the backing 48 and is formed by anelectroplating process to the conductive material transfer layer 40.

In another embodiment the male imprint tool 50 is formed directly on thefemale tool 321 (FIG. 3 c) by applying an electroless activating step(140) to the female tool followed by electroforming a male tool 48 (144)onto the female circuit imprint tool master 22 a to form the assemblyshown in FIG. 5A. The male tool may then be removed from the femaleimprint tool master (148). The conductive material transfer material 40is then further applied (152) onto the male imprint tool. The resultantmale circuit imprint tool is the same as shown in FIGS. 6 and 6 a.

While in the preferred embodiment of the present invention anelectroplating process was described for forming the conductive materialtransfer layer 40 on the imprint tool and the imprint tool master, itwill be understood by those skilled in the art that other techniques canbe employed such as electroless plating, vapor deposition and metalflame spraying.

A further embodiment is shown in FIG. 7 wherein the female circuitimprint tool master is directly formed photolithographically on a planarsubstrate 700. In one nonlimiting embodiment a multilayer female circuitimprint tool master is formed from separate layers of photoresist 701,702 using unique phototools for each layer. The layers are formedsequentially upon the substrate 700 in separate photolithographic steps.The process is the same as described above for preparation of the femaletool (124,126) but rather than etching the substrate to form a femaleimprint tool master, the form of the circuit imprint tool master isbuilt up of photoresist and the male tool is then formed thereon, ametal circuit imprint tool 703 may be formed thereon using eitherelectroforming or electroplating (132) through the openings in thephotoresist. After forming, the male circuit imprint tool is removedfrom the substrate and coated with the transfer conductive materiallayer 40 using techniques already described.

In another embodiment (not shown) the male circuit imprint tool isformed directly in a blank of mold material using a photolithographicprint and etch process similar to that used to form the female imprinttool master.

In one embodiment as seen in FIG. 8, the inventive method continues byapplying a thin layer of adhesion promote coating 46 (160) on thesurface of the conductive material transfer layer 40 of the male circuitimprint tool 50. In one embodiment the adhesion promote coating 46 isformed by bathing the tool 50 in a water base oxidizing bath to form ahighly adherent dendritic oxide coating on the conductive materialtransfer layer 40. This wet chemical oxidation treatment prepares theconductive material transfer layer 40 for lamination to the substrate 80(FIG. 10).

In another embodiment the preparation of the male circuit imprint tool906 is completed by removing the conductive material transfer layer 905and adhesion layer 901 at the prominences of the circuit imprint 902,903, 904 (162) as shown in FIG. 9. Such removal can be accomplishedusing standard manufacturing processes such as mechanical abrasion,buffing or chemical etching. In another embodiment the conductivematerial transfer layer is selectively removed from the prominences by aphotolithographic print and etch process. Thereby some of theprominences will have the conductive material removed as shown in902-904 and other prominences, not shown, will still be coated with theconductive material transfer layer.

In other embodiments shown in FIG. 9 a a multilayer male imprint tool 48is prepared by removing the conductive material transfer layer 40 andthe adhesion promoting coating 46 selectively from prominences on thecircuit imprint tool. As shown the conductive material transfer layerhas been removed from two of the prominences 51, 52 and remains on theprominence 53.

A nonlimiting example of the process used to realize circuits containingmicrotraces and microvias is illustrated in the flowchart shown in FIG.18 and is discussed in detail below, where reference numbers enclosed inparentheses refer to the flow chart.

When the conductive material transfer layer 40 has been coated with anadhesion promotion layer 1001 such as a dendritic oxide, the tool 1000(180) is placed upon an uncured deformable circuit substrate 1004 in ahigh heat deflecture plastic molding machine, such as a laminating press(182) used in making multi-layer circuits (not shown) which under heatand pressure causes a blank 1003 (184) to be formed as shown in FIG. 10.Nonlimiting examples of the circuit substrate materials includethermoplastic polymeric material, thermoset material, or uncuredceramics. The conductive material transfer layer 1002 is laminated withthe adhesion promotion layer 1001 to the circuit substrate 1004. Theconductive material transfer layer is transferred from the circuitimprint tool 1000 to the substrate 1004 creating a conductive materiallayer both on the surface 1008 of the substrate as well as on the walls1005 of the grooves formed from the prominences 1009 of the circuitimprint tool. The circuit imprint tool 1000 may then be removed from thesubstrate 1004 leaving a substrate similar to that shown in FIG. 11(186). In another embodiment the substrate may consist of both a curedand uncured layers such as used in conventional multilayer printedcircuit board manufacturing. Surfaces of the cured layers may includeconductive material such as traces of an inner layer of a printedcircuit board. In this embodiment the circuit imprint tool is placedupon an interposed uncured prepreg layer atop the cured inner layer.Selected prominences 1012 of the circuit imprint tool may be alignedwith conductive material of the inner layer 1006 thereby aligning theresultant vertical conductive material 1010 with the conductive material1006 providing a means for creating a micro via creating a connectionfrom the surface to an interior layer of the resultant circuit.

Next, referring to FIG. 11, in one embodiment after removal of thecircuit imprint tool from the substrate, the surface conductive materialtransfer layer areas 64 interconnecting the microtraces 72-77 areremoved by applying an etch resist not shown (188) within the grooves61-63 using a squeegee, abrasive removal of smudged edge resist from thesurfaces 64 and open etching to form the circuit 1200 shown in FIG. 12.

In another embodiment the surface areas are selectively removed by aprint and etch (190) process thereby forming trace features 81 (FIG. 12a) on the surface of the substrate 80 as well (192). The print and etchprocess is known to those skilled in the art. The conductive materialwithin the grooves 61 to 63 may be protected during such a print andetch process by first plugging with a squeegeed on etch resist aspreviously described.

In another embodiment, microvia interconnect between the surface and aninner layer conductive material is formed using a standard desmear (194)and conductive backfill processes (196) familiar to one skilled in theart. The resultant circuit, shown in FIG. 12 includes an inner layerconductive material 1201 that is connected to the surface 1210 of thecircuit by connection to the vertical walls 1203, 1204 of an imprintedmicrovia through a conductive fill material 1209. Non-limiting examplesof a conductive fill material 1209 include conductive material formed bydesmear, electroless and plating as in conventional printed circuitboard manufacturing, conductive adhesives or conductive polymers,conductive material that is applied through other techniques such asvapor deposition, electroless deposition or metal flame deposition allknown in the art. The circuit further contains vertical traces 1205,1206, 1207, 1208 which are all formed simultaneously with the microviasusing the imprint process as described above.

In other embodiments, shown in FIG. 12 a, the techniques alreadydescribed can be used to selectively etch surface areas of the circuit90 leaving surface traces 81, vertical microtraces 72 that connectsurface conductive material 81 with inner layer conductive material 65embedded in the circuit substrate 80, multilayer vertical microtraces 73that do not connect to an inner layer conductive material, verticalmicrotraces that are in pairs 74, 75 that may be selectively locatedover embedded inner layer conductive material 82 and verticalmicrotraces 76 in which the paired vertical microtrace has beenselectively etched away leaving a vertical wall 77.

In another embodiment application of the techniques described createredundant vertical microtraces. The same artwork that is used inmanufacturing conventional circuitry with horizontal traces in multiplelayers is used to produce the female imprint tool master and from thatthe male imprint tool. It is seen that for each horizontal trace in theconventional design, there will be produced a pair of vertical traces inthe imprint embodiment in which the transfer conductive material layeris removed from the prominences of the male imprint tool prior totransfer lamination to the circuit. Left intact, each pair of verticaltraces interconnects the same points as in the conventional design.However now instead of a single horizontal trace there are a pair ofvertical microtraces thereby providing a redundant interconnect.Examples of such redundant conductive material are represented in FIG.12. Microtraces prepared by either the squeegee and etch processpreviously described or by a selective print and etch process alsopreviously described in which both of the pair of vertical traces isprotected by an etch resist will result in redundant pairs. Two sets ofsuch redundant pairs are shown 1205, 1206 represent a redundant pair and1207, 1208 represent a second redundant pair.

Thus, it is seen there is provided a new and improved method ofmanufacturing three-dimensional circuits that include high aspect ratiomicrotraces. Additionally, a number of unique and useful interconnectconfigurations are possible using combinations of the layers fabricatedusing the inventive method or in combination with conventional layerconfigurations.

FIG. 13 shows balanced 94 and unbalanced 92, 96 microstrip transmissionline embodiments using the microtrace structures imprinted in plasticlayer 86 deposited on dielectric layer 84 grown on top of ground plane82 deposited on substrate 80. Adjustment of the thickness and dielectricconstant of the dielectric layer allows the intrinsic impedance of thetransmission lines to be adjusted over a wide range. Adjustment of traceseparation and the dielectric filler 88 in the balanced structuresimilarly affects transmission line properties.

FIG. 14 shows a three-layer circuit embodiment that includes nearlyfully enclosed shielded microtraces. Lower shields 101-103 are realizedusing conventional imprinting techniques to fully coat the imprintedgrooves with conductive material. These grooves are backfilled withdielectric 88 and a second plastic layer 86 is attached to the topsurface. The inventive method is used to fabricate microtraces that areoffset with respect to the first layer pattern to center the middlemicrotraces 104-106 over the lower shield. After backfilling withdielectric material, a third plastic layer 100 is attached to thecomposite and the inventive method is again employed to form uppershields 107-109. In another embodiment the fully enclosed shieldedmicrotraces may be intermixed in the same construction with non-shieldedmicrotraces using the technique described above to selective removeconductive material from the prominences through a photolithographicprint and etch process.

In another embodiment shown in FIG. 16, a grid electrode structure isfabricated using the inventive method that includes first layermicrotraces 114-116 imprinted in substrate 80 beneath second layermicrotraces 111-113 fabricated in a second layer. FIG. 15 shows a crosssection of the structure which exhibits extremely small fringingcapacitance between x- and y-directed microtraces.

In another embodiment shown in FIG. 16 a, the vertical microtracescrossing in adjacent levels at approximately right angles areselectively interconnected at junctions. In one embodiment a connectionis made between crossed vertical microtrace 119 and 120 at theintersection through addition of an interconnect conductive material121. Non-limiting examples of interconnect conductive material includesolder, other malleable metals, conductive adhesive and simple platedprotrusions the same conductive material used to make the verticalmicrotraces 119 and 120. It should be noted that both verticalmicrotraces 119 and 120 are embedded in a typically dielectric substrateupon which the imprinting is done. Similarly, vertical microtraces 119and 123 are selectively not connected at the junction 124 by priorselective etching of the transfer conductive material from the imprinttool at the anticipated points of the junction prior to imprinting. Theadditional process steps required to implement this unique circuitstructure are described below and involve the preparation of a thin,separate upper microtrace layer which is subsequently bonded to a lowermicrotrace layer formed on a thick circuit substrate as describedpreviously.

FIG. 19 shows a cross section of an embodiment of a three-dimensionalcircuit 200 fabricated using the inventive method wherein a twodimensional double level electrode structure is produced wherein theelectrodes on different levels are electrically isolated from each otherand no gap or overlap exists between the surface projections ofelectrodes on different levels. In FIG. 19 traces 202 have been coatedwith conductive material and the intervening surface conductive materialhas been removed using an etch process that results in the slightvertical etching of the vertical trace conductive material, and thetraces have subsequently been backfilled with plating resist 204 appliedin one embodiment using a squeegee. Nonlimiting alternative applicationtechniques include photolithography and screen printing. In FIG. 20 thesubstrate surface is plated to form surface electrodes 206 that areelectrically isolated from the traces 202 by gaps 208 inherent in theformation of the traces caused by the lateral etching that accompaniesthe removal of the original surface conductive material. Note that thegaps 208 formed in the imprinting process also form inherent solder damsthat help to confine solder to the trace grooves in the finishedcircuit. In FIG. 21 the plating resist has been removed resulting in thethree-dimensional circuit structure having one possible surfaceconfiguration as shown in the top view in FIG. 22. Trace elements 202and surface elements 206 can be separately interconnected diagonally toform a two dimensional array of capacitive sensors for use in touchscreens.

As shown in FIG. 23, a circuit imprint tool for the upper layer 2300 isplaced upon an uncured deformable upper circuit substrate 2304 in a highheat deflecture plastic molding machine, such as a laminating press usedin making multi-layer circuits (not shown) which under heat and pressurecauses a blank 2303 to be formed. Nonlimiting examples of the circuitsubstrate materials include thermoplastic polymeric material, thermosetmaterial, and uncured ceramics. The conductive material transfer layer2302 is laminated with the adhesion promotion layer 2301 to the circuitsubstrate 2304. The conductive material transfer layer is transferredfrom the circuit imprint tool 2300 to the substrate 2304 creating aconductive material layer both on the surface 2308 of the substrate aswell as on the walls 2307 of the grooves formed from the prominences2309 of the circuit imprint tool. At the nominal pressures experiencedin the molding machine a thin web of substrate material 2305 will remainat the tips of the prominences 2309 of the circuit imprint tool.

The circuit imprint tool 2300 may then be removed from the substrate2304 leaving an upper circuit substrate similar to that shown in FIG. 24a. A permanent dielectric etch resist material 2405 is then applied tofill the grooves 2401, 2402, 2403 in substrate 2304, resulting in thestructure shown in FIG. 24 b. The dielectric material can be applied,for example, using a squeegee, dry film processing, wet coating orscreen printing. The circuit is then subjected to a metal etch whichremoves the surface conductive material 2404. The thin web of substratematerial 2305 is then removed, resulting in the upper circuit substrateillustrated in FIG. 24 c containing microtraces 2411-2416. Grooves 2501and 2502 that align with the microtraces in the lower substrate areetched in the bottom of the upper circuit substrate using standard printand etch methods, as shown in FIG. 25 which illustrates microtrace 2411in FIG. 24 c rotated by 90 degrees.

FIG. 26 a shows an exploded view of the two-layer structure in whichmicrotrace 2602 in the upper circuit substrate 2601 is intended to beelectrically connected to microtrace 2605 in the lower circuit substrate2600, but microtrace 2602 is to remain electrically insulated frommicrotrace 2604 in the lower circuit substrate. Notches 2603 and 2613are etched in microtrace 2602 using standard print and etch techniquesfamiliar to one skilled in the art, which notches align with notches2606 and 2616 similarly etched in microtraces 2604 and 2605,respectively. A block of electrically conductive interconnect material2610 is notionally illustrated to show how microtraces 2602 and 2605 areto be interconnected. FIG. 26 b shows etched notches 2613 and 2616filled with a conductive material such as solder paste that will bejoined to effect the interconnection between microtraces 2602 and 2605.Etched notches 2603 and 2606 are either unfilled or, optionally, filledwith a dielectric material to maintain the electrical isolation ofmicrotraces 2602 and 2604. FIG. 26 c shows the integrated assembly inwhich the conductive material filling etched notches 2613 and 2616 hascoalesced to effect the electrical connection of microtraces 2602 and2605. The air- or dielectric-filled notches 2603 and 2606 (not shown forclarity) between microtraces 2602 and 2604 form the cavity 2620 thatmaintains the electrical isolation of microtraces 2602 and 2604.

SUMMARY

Imprinting tools and processes for making such tools, circuitry thatincludes narrow, high aspect ratio traces having reduced parasiticcapacitance to adjacent circuit features and processes for making suchcircuitry using the imprinting tools are described. Those skilled in theart will appreciate that various adaptations and modifications of thepreferred embodiments can be configured without departing from the scopeand spirit of the invention. Therefore, it is to be understood that theinvention may be practiced other than as specifically described herein,within the scope of the appended claims.

What is claimed is:
 1. A method of making a three dimensional circuit,comprising: a) forming a three dimensional male circuit imprint toolhaving a removable coating of conductive material on a surface havingprominences; b) coating said conductive material with a thin layer of ahighly adherent material; c) selectively removing said adherent materialand said conductive material coating from prominences on said threedimensional male circuit imprint tool, wherein selectively removing saidconductive material coating from prominences is accomplished usingeither mechanical abrasion or chemical etching, d) pressing said threedimensional male circuit imprint tool into a deformable plastic materialto deform the plastic material and transfer the removable conductivematerial coating to the deformable plastic material resulting in asubstrate having a surface with a plurality of conductively coatedindentations disposed therein where said indentation are at least oneselected from grooves and pits; e) admitting to said plurality ofconductively coated indentations an etch resistant material; and f)etching a desired electrical circuit pattern in the surface of saidconductive material.
 2. A method of making a three dimensional circuitaccording to claim 1, wherein the removable conductive material coatingis at least one selected material selected from: nickel, copper, gold,and indium tin oxide (ITO).
 3. A method of making a three dimensionalcircuit according to claim 1, wherein said step of forming threedimensional male circuit imprint tool comprises formation from apredecessor female tool.
 4. A method of making a three dimensionalcircuit according to claim 3, wherein said step of forming a malecircuit imprint tool comprises: a) coating said female predecessormaster tool with a low adhesion material; b) depositing a thin layer ofconductive material on the coated female processor master tool; and c)separating said thin layer of conductive material from said femalepredecessor master tool to form the three dimensional male circuitimprint tool.
 5. A method of making a three dimensional circuitaccording to claim 3, wherein said step of forming a male circuitimprint tool comprises: a) coating said female predecessor master toolwith a low adhesion material; b) depositing a thin layer of conductivematerial on the coated female processor master tool; c) attaching alayer of backing material to the layer of conductive material; and d)separating said backing layer and said thin layer of conductive materialfrom said female predecessor master tool to form the three dimensionalmale circuit imprint tool.
 6. The method of claim 5 wherein the backingmaterial comprises a metal layer electroplated on the thin layer ofconductive material.
 7. The method of claim 5 wherein the backingmaterial comprises a plastic layer molded or laminated to the thin layerof conductive material.
 8. A method of making a three dimensionalcircuit according to claim 1, wherein said step of forming a malecircuit imprint tool comprises direct formation in a blank of circuitimprint material.
 9. A method of making a three dimensional circuitaccording to claim 8, wherein direct formation comprisesphotolithography and chemical etching.
 10. A method of making a threedimensional circuit according to claim 8, wherein direct formationcomprises photolithography and electroforming.
 11. A method of making athree dimensional circuit according to claim 1, wherein said highlyadherent material is an oxide of the material primarily forming theremovable conductive coating.
 12. A method of making a three dimensionalcircuit according to claim 4 or claim 5, wherein said low adhesionmaterial is silver, a graphite material or surface passivation.
 13. Amethod of making a three dimensional circuit according to claim 1,wherein said step of admitting includes removing selectively asufficient quantity of said etch resistant material from individual onesof the grooves to expose the conductive material surface in a topportion thereof.
 14. A method of making a three dimensional circuitaccording to claim 13, wherein the step of etching a pattern in saidconductive material includes removing the exposed conductive materialsurface from the top portion of the selected individual ones of thegrooves to form spaces between the top surface of the resulting circuitand the top portions of the grooves to define solder dams within saidgrooves.
 15. A method of making a three dimensional circuit according toclaim 1, wherein said step of pressing includes: a) heating said plasticmaterial to a sufficient temperature to enable the material to deformunder pressure; b) stamping said plastic material with said male circuitimprint tool; c) whereby a substrate blank is formed having a pluralityof indentations coated with conductive material disposed within thesurface thereof where said indentations are at least one selected fromgrooves and pits.
 16. A method of making a three dimensional circuitaccording to claim 15, wherein said plastic material is a thermoplasticmaterial.
 17. A method according to claim 16, wherein said thermoplasticmaterial is a platable thermoplastic material selected from the group ofpolyethersulphone, polyetherimide, polybutylene terephthalate (PBT), orpolyether ether ketone (PEEK).
 18. A method according to claim 15,wherein said plastic material is a thermoset plastic, such as epoxythermoset polyetherimide, or a polyester based composite of saidthermoset plastic.